Cache Write Policies

Last updated Nov 8, 2022 Edit Source

How do we keep memory updated while writing on the cache?

Every write to the cache will lead to subsequent writes to the rest of the memory hierarchy, L1 -> L2 -> Main Memory -> Disk.

• Memory coherency

• High bandwidth requirement, every cache write results in high latency
• Memory becomes slow as size increases

Only write memory to rest of the memory hierarchy on cache replacement.

Maintain the state of each cache line as the following

• Invalid: not present
• Clean: present and unmodified
• Dirty: present and modified Update the state bit on modification.

• Cache Coherence: in multi-processors where each core maintains its own level of cache, if one core needs to access the data that has been modified by another core, they will get the stale data from memory as updated data is still in that core’s own cache and has not been propagated.
• Coherent I/O: I/O devices are able to use DMA and access stale copies of data in main memory.